In the manufacturing of semiconductor devices, particularly DRAM devices having FETs, the need for ever-increasing density of electrical contacts makes it desirable to fabricate borderless contact structures. The use of cap structures which overhang the sides of the capped region (beanie structures) facilitates processing of borderless contacts. However, the conventional method for forming a beanie structure involves several film deposition and etching steps. Steps in a typical process are shown in FIGS. 1A-1E. The structure to be capped (e.g. an FET gate structure 2 on a substrate 1, as in FIG. 1A) has an oxide cap layer 2a formed at the top of the structure. A layer 3 of sacrificial material is deposited on the substrate, and then planarized and etched so that its top surface is below layer 2a (FIG. 1B). A conformal layer 4 (typically silicon oxide) is deposited on the sacrificial material and over the gate structure (FIG. 1C). This layer is then etched to form structures 5, resembling spacers used in conventional FET processing, on the upper sidewalls of the gate (FIG. 1D). The sacrificial layer 3 is then removed, leaving a beanie structure, comprising structures 5 and cap layer 2a, on the gate structure 2 (FIG. 1E). This process, which requires film deposition, planarization and etching, is cumbersome and costly.
Accordingly, there is a need for a process for fabricating a beanie structure with a reduced number of steps, so that the advantages of using beanie structures may be realized in a manufacturing environment.